Deploy to any 32-bit processor.

The Logic-Based Network

The trained LBN is represented as a set of propositional logic clauses — compact, deterministic, and directly executable. Unlike a neural network weight file, the LBN does not require floating-point matrix operations to run. It operates through bitwise logic on integer data: fast on any processor that can handle 32-bit operations, and naturally suited to the constrained environments where edge AI actually lives.

The LBN is generated specifically for your training data and your target classification task. It is not a general-purpose model compressed down to fit; it is a model built from the ground up for the problem.

The inference engine

The inference engine is the runtime that executes the LBN on the target hardware. Written in C, it has no external dependencies and compiles cleanly against standard embedded toolchains — including ARM GCC, RISC-V GCC, and Espressif's IDF. The engine is optimised for the bitwise operations the LBN uses, which is why it achieves the inference speeds it does on modest hardware.

Memory allocation is static. There is no dynamic allocation at inference time — which matters in RTOS environments and bare-metal deployments where heap fragmentation is a genuine engineering concern.

Build configuration and example code

The SDK includes a build configuration appropriate for the target architecture, alongside example code demonstrating initialisation, feature ingestion, and inference call structure. The examples are written to be adapted rather than copied wholesale — they show the integration pattern clearly without making assumptions about your firmware architecture.

Integration documentation accompanies the code, covering the expected input format, output classification schema, platform constraints, and guidance on fitting the inference call into an existing firmware loop. Engineers familiar with embedded ML frameworks will find it considerably more direct than most.

Arm Cortex-M

The primary target for most embedded AI deployments. Cortex-M0 through M7 are all supported, spanning the range from ultra-low-power IoT sensors to more capable control applications. The LBN's bitwise execution model maps well onto the Cortex-M instruction set — no FPU required, and inference fits comfortably within the cycle budgets of real-time tasks.

Arm Cortex-M deployment details →

RISC-V

Adoption in embedded systems has accelerated significantly, particularly in cost-sensitive designs and custom silicon. The SDK compiles cleanly for RISC-V RV32 targets, including common SoCs from Espressif and SiFive lineages.

RISC-V deployment details →

ESP32

The ESP32 family is a practical target for connected edge AI: dual-core architecture, integrated wireless, and a development ecosystem (ESP-IDF) engineers already know. The SDK integrates with ESP-IDF directly with no separate build system required.

ESP32 deployment details →

x86

For edge servers, industrial gateways, and development workflows, the SDK also targets x86. Useful both for rapid prototyping on a workstation before deploying to an MCU, and for deployments where the target is a compact industrial PC rather than a microcontroller.

x86 deployment details →

Code example

The essential pattern — initialise once, feed features, read result:

#include "lbn_inference.h"

/* Initialise the inference engine (call once at startup) */
lbn_ctx_t ctx;
lbn_init(&ctx, &model_params);

/* In your sensor processing loop */
int32_t features[FEATURE_COUNT];
collect_features(features);           /* your sensor/signal processing */

lbn_result_t result;
lbn_infer(&ctx, features, &result);   /* classify */

if (result.class_id == CLASS_ANOMALY) {
    trigger_alert();
}

The full SDK documentation covers the complete API surface, including batch inference, confidence thresholds, and output interpretation.